1. Field of the Invention
The present invention relates to reliability analysis for integrated circuit designs, and more particularly interconnect and transistor reliability analysis for deep sub-micron integrated circuit designs.
2. Description of the Related Art
In deep sub-micron designs, metal interconnects and transistors subject to ever increasing current densities and temperature can wear-out over a period of time causing chip-level failures. Electromigration is a known interconnect wear-out mechanism caused due to the movement of metal atoms under high current and thermal gradients. Time-dependant dielectric breakdown (TDDB) in transistors can occur due to continuous application of electric fields across the oxide layer often resulting in permanent circuit failure. Similarly, hot carrier injection (HCI) effects in transistors that affect carrier mobility are often caused due to carrier trapping inside the gate oxide or the SiO2 layer, due to the continuous application of high drain to source bias. In addition, bias temperature instability (BTI) that manifests itself at high temperatures as shift in threshold voltage in transistors causes temporary timing failures in the design. Such failure mechanisms often place constraints on the DC current density that an interconnect line can support, or the maximum electric field that a transistor can support. In addition, Joule heating can reduce mean time to failure (MTTF) of interconnects and transistors, and can place constraints on the root mean squared (RMS) current density that an interconnect line or a transistor can support.
Accurately solving DC and RMS currents in each interconnect segment via circuit simulation can be a compute intensive-task for large integrated circuit (IC) designs. Known approaches have attempted to reduce the complexity of the analysis by filtering out from the analysis nets that drive small capacitance loads. In deep submicron designs, however, the ever increasing component density can cause thermal gradients to induce failures in unsuspecting nets adjacent to high current nets. Previous work has also demonstrated that a static linear analysis approach makes this a tractable problem, and produces results within acceptable error bounds.